The present invention relates generally to semiconductor devices, and more specifically to fabrication methods for BiCMOS devices.
BiCMOS devices combine both bipolar and metal oxide semiconductor (MOS) transistors on a single integrated circuit. Bipolar and MOS devices each offer unique performance advantages which, when combined into a single package, produce a device with distinct advantages over either technology by itself. Such advantages are discussed in A. R. Alvarez, BiCMOS Technology and Applications, pp. 1-17, which is incorporated herein by reference.
Known methods for fabricating BiCMOS devices are described in, for example, U.S. Pat. No. 4,764,480 to Vora, U.S. Pat. No. 4,868,135 to Ogura et al. and in A. R. Alvarez, BiCMOS Technology and Applications, pp. 63-119, all of which are incorporated herein by reference for all purposes.
It is frequently desirable to fabricate BiCMOS devices with one or more capacitors formed on the substrate in addition to the bipolar and MOS transistors. Such capacitors commonly consist of a first polysilicon layer, a layer of oxide or other dielectric on the first polysilicon layer, and a second polysilicon layer on the oxide layer. This type of interpoly capacitor is particularly desirable because of its low parasitic capacitance.
A known method for fabricating an interpoly capacitor in a BiCMOS device is described in A. R. Alvarez, supra, at pp. 115-119. Alvarez describes a method wherein a first layer of polysilicon is formed on an oxide region of the substrate to form the capacitor, the same layer of polysilicon being formed on the MOS regions of the substrate to form gate electrodes. An interlevel dielectric (ILD) is formed over the first polysilicon region, using either oxide or oxide/nitride combination. A second polysilicon layer is then formed over the ILD layer to form the second terminal of the capacitor.
It should be noted that the device formed by the method disclosed in Alvarez does not utilize a polysilicon emitter contact for the bipolar transistor. In some advanced BiCMOS fabrication processes, a polysilicon emitter contact is formed over the bipolar base and an emitter diffused from the polysilicon emitter contact. An example of such a process is disclosed in Bastani, "Advanced One Micron BiCMOS Technology For High Speed 256K SRAMs", the full disclosure of which is incorporated herein by reference. Bastani describes a BiCMOS fabrication process wherein an oxide layer forming the interpoly dielectric is formed over the bipolar base. The oxide layer is then etched over a portion of the bipolar base to create an emitter window. A second polysilicon layer is then formed over the oxide layer, including in the emitter window, and the second polysilicon layer is etched to form the emitter contact.
It has been found that in forming a polysilicon emitter contact through an emitter window using a process such as that just described, it is extremely important to ensure the silicon surface of the base region in the emitter window remains free of oxide when the polysilicon layer is formed. Typically, over a short period in an oxygen-containing atmosphere, the silicon surface will tend to grow a thin layer of native oxide. Therefore, just before deposition of the second polysilicon layer, a very short etching step is conducted to remove this native oxide from the emitter window.
This short etching step, however, has led to difficulties when a capacitor like that disclosed in Alvarez is desired on a BiCMOS device with a polysilicon emitter contact like that of Bastani. To form such a device, an oxide layer is formed over the first polysilicon terminal of the capacitor as well as over the bipolar base, allowing both the interpoly dielectric of the capacitor as well as the emitter window to be formed from the same oxide layer. The polysilicon layer used to form the emitter contact may be used also to form the second polysilicon terminal of the capacitor.
However, such a process has suffered from the inability to prevent etching of the oxide layer of the interpoly capacitor during the short etching step to remove native oxide in the emitter opening before deposition of the second polysilicon layer. It is critical that the thickness of the interpoly dielectric be maintained within a certain range in order for the capacitor to perform properly. The etching step for removing the oxide in the emitter window will also tend to remove some oxide needed for the interpoly dielectric, making it difficult to control the interpoly dielectric thickness.
For these reasons, a method of fabricating an interpoly capacitor on a BiCMOS device is desired which allows formation of a polysilicon emitter contact, but which allows etching of the oxide in the emitter window for such a contact while maintaining the thickness of the interpoly dielectric layer for the capacitor. The method should minimize process steps, preferably allowing the same oxide layer used for the interpoly dielectric to be used for forming an emitter window in which the polysilicon emitter contact is formed.